NVIDIA
Hardware debug platforms for next-generation AI/HPC systems.
DFX, scan/JTAG state capture, pre-silicon verification, and debug tooling, focused on making complex silicon observable and repeatable to debug.
Selected outcomes
Measured impact from silicon DFT work.
Quantified results from DFT methodology and test-economics work on high-volume silicon (Intel, 2021-2024).
Current role
Senior DFX Methodology Engineer
- DFX methodology and DFT for AI/HPC silicon platforms (IEEE 1149.1 / 1500 / 1687, JTAG / IJTAG).
- State capture and observability: scan dump, RAM dump, IO BIST, memory BIST, and DFD flows.
- Internal scan-debug GUI tooling used across multiple engineering teams.
- Pre-silicon verification and post-silicon bring-up / debug.
- DFX security and test-access discipline for complex parts.
- Cross-team enablement turning low-level silicon behavior into repeatable workflows.
Instruments
What “observable silicon” actually means.
The access mechanisms that turn otherwise-invisible internal behaviour into something you can read out and debug.
Scan / JTAG
Shift internal state out a serial path (IEEE 1149.1).
Die & package
Reach state the package hides: lid, die, interposer.
Memory / IO BIST
Built-in self-test drives arrays and reads back results.
Capture & trace
Deterministic capture, replay, and root-cause workflows.
Earlier work
Systems thinking before silicon observability.
Product Development Engineer: test methodology, RTL, and test programs (C#/Perl) for repair, raster, and scan features; ATPG/coverage analysis and large-scale JMP data analysis. Improved scan-testing efficiency and reduced test time ~10%, boosted spec-validation efficiency ~15% and testing accuracy ~20%, and drove a ~20% yield increase with multi-million-dollar annual test-cost savings.
Materials-science and additive-manufacturing research at Zeda (formerly PrinterPrezz), Northeastern University, and DMRL: a systems view of reliability, from physical defects to test economics.
M.S. Mechanical Engineering (materials science), Northeastern University; B.Tech Materials Science & Engineering, IIT Kanpur.
Next step