NVIDIA
Hardware debug platforms for next-generation AI/HPC systems.
DFX, scan/JTAG state capture, pre-silicon verification, and debug tooling — focused on making complex silicon observable and repeatable to debug.
Current role
Senior DFX Methodology Engineer, AI Hardware / Silicon Debug Platforms
- DFX methodology and DFT for AI/HPC silicon platforms (IEEE 1149.1 / 1500 / 1687, JTAG / IJTAG).
- State capture and observability: scan dump, RAM dump, IO BIST, memory BIST, and DFD flows.
- Internal scan-debug GUI tooling used across multiple engineering teams.
- Pre-silicon verification and post-silicon bring-up / debug.
- DFX security and test-access discipline for complex parts.
- Cross-team enablement turning low-level silicon behavior into repeatable workflows.
Earlier work
Systems thinking before silicon observability.
2018 – 2024
Intel
DFT feature integration for Intel SoCs, ATE test plans, ATPG/coverage analysis, JTAG/MBIST/scan compression. Drove ~20% scan-efficiency improvement, ~15% test-cost reduction, ~10% coverage gain, and $1M+ annual cost reduction at sub-250 DPPM.
2020 – 2021
Materials & manufacturing
Materials science and manufacturing work underpinning a systems view of reliability — from physical defects to test economics.
2015 – 2021
Education & leadership
Co-Founder of Angelica International School. MS Mechanical Engineering, Northeastern University; BTech Materials Science & Engineering, IIT Kanpur.