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NVIDIA
DFX, scan/JTAG state capture, pre-silicon verification, and debug tooling, focused on making complex silicon observable and repeatable to debug.
Selected outcomes
Quantified results from DFT methodology and test-economics work on high-volume silicon (Intel, 2021-2024).
Current role
Instruments
The access mechanisms that turn otherwise-invisible internal behaviour into something you can read out and debug.
Shift internal state out a serial path (IEEE 1149.1).
Reach state the package hides: lid, die, interposer.
Built-in self-test drives arrays and reads back results.
Deterministic capture, replay, and root-cause workflows.
Earlier work
Product Development Engineer: test methodology, RTL, and test programs (C#/Perl) for repair, raster, and scan features; ATPG/coverage analysis and large-scale JMP data analysis. Improved scan-testing efficiency and reduced test time ~10%, boosted spec-validation efficiency ~15% and testing accuracy ~20%, and drove a ~20% yield increase with multi-million-dollar annual test-cost savings.
Materials-science and additive-manufacturing research at Zeda (formerly PrinterPrezz), Northeastern University, and DMRL: a systems view of reliability, from physical defects to test economics.
M.S. Mechanical Engineering (materials science), Northeastern University; B.Tech Materials Science & Engineering, IIT Kanpur.
Next step