Aditya Morey.

Driving DFX methodology for AI and high-performance computing hardware, with a focus on debug visibility, secure test access, silicon bringup, and product readiness.

• Implement state-of-the-art test access mechanisms, including IEEE 1149.1, IEEE 1500, IEEE 1687, JTAG/IJTAG, IO BIST, memory BIST, scan dump, and array dump solutions.
• Architect next-generation DFT methodologies for AI/HPC platforms where diagnosability, traceability, and reliability are product-critical.
• Pioneer robust DFX security methodologies to protect resilience and integrity across world-class AI hardware systems.
• Mentor junior engineers in advanced test design strategies, optimizing for performance, cost efficiency, and silicon quality.
• Spearhead pre-silicon verification for critical AI-enabling features like scan dump and RAM dump on next-generation NVIDIA platforms.
• Lead post-silicon bringup and debugging for flagship AI and HPC hardware, accelerating product readiness and reliability.
• Collaborate with global teams to optimize scan debug GUI tools across NVIDIA's AI product ecosystem.

Owned testability, manufacturability, validation, and data-driven product development for advanced Intel process and server products.

• Spearheaded DFT feature integration for Intel SoCs, improving SCAN testing efficiency by 20% and reducing test costs by 15%.
• Led ATE test-plan development for high-performance SoCs, increasing test coverage and reducing defect rates below 250 DPPM.
• Conducted ATPG and test coverage analysis using industry-standard tools, increasing coverage by 10% and improving yield.
• Developed and optimized JTAG, MBIST, and Scan Compression methodologies, contributing to $1M+ annual cost reduction.
• Partnered with Test Engineering on silicon bringup/debug, test pattern optimization, and faster debug workflows.

Built advanced manufacturing and materials workflows for 3D printed medical devices, connecting research, process optimization, and measurable product quality.

• Pioneered nanotextured coatings for spinal implants, improving surface integration by 50% and biocompatibility by 50%.
• Simulated and optimized 3D printing processes with Autodesk Netfabb and DigiMat, reducing prototyping time by 25%.
• Characterized Titanium and PEEK nanotextured implants, achieving a 30% increase in quality consistency.
• Worked with engineering teams to refine manufacturing processes, delivering a 20% yield increase and 15% performance improvement.

Co-founded an education initiative for underprivileged students, combining mission-driven operations, sustainable business model design, and long-horizon community impact.

• Founded the school in 2015 to provide free education to underprivileged students.
• Developed an investor-supported operating model to strengthen financial stability.
• Implemented teaching methods designed to improve engagement and create a supportive learning environment.

Applied product engineering and additive manufacturing rigor to implant design, manufacturability, quality validation, and cost reduction.

• Designed and optimized a 3D CAD model for a titanium hip implant, reducing production time by 20% and cost by 15% through selective laser melting.
• Improved manufacturability by 15% through validation of implant performance against quality standards and specifications.