Work
Silicon debug, DFX, scan/JTAG, pre-silicon verification, and debug platforms for AI/HPC systems.
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Aditya Morey · NVIDIA · AI Hardware DFX
Debug and observability systems that turn hidden AI/HPC silicon state into repeatable root-cause workflows.
JTAG/IJTAG, MBIST, IO BIST: engineered access into otherwise invisible silicon state.
Deterministic debug platforms shared across teams, not one-off scripts.
Built into the silicon up front, not bolted on after the bug.
In one line
I build and study debug, verification, and observability systems for complex compute, turning low-level silicon behavior into repeatable, inspectable workflows engineers can actually use.

Focus areas
Latest writing
Manifesto
Frontier AI silicon and frontier AI agents fail the same way: in the dark, between layers, under pressure. Observability is not a dashboard. It’s the thing that turns those failures into root-cause workflows.
Scan paths, JTAG/IJTAG, MBIST, IO BIST: engineered access into otherwise invisible behaviour.
Tooling shared across teams: deterministic capture, replay, and root-cause workflows.
Tracing, escalation checkpoints, replay: the same primitives, applied to autonomous systems.
Start here

New · book · first research edition
Capability without engineered evidence is not deployment readiness. Why autonomous AI needs state capture, replay, and escalation before it can be trusted: silicon debug discipline, translated for agentic systems.
Publication hub
A curated technical publication surface for essays, frameworks, and labs on observability for complex compute systems.
Who I talk to
Public artifacts
demos / papers / essays / inspectable
Interactive visualizer for scan-chain state movement, TAP-style control flow, and state-capture intuition.
OpenPublic demo showing how observability changes fault isolation and root-cause workflow.
OpenPublished framework for reasoning about useful AI output under latency, reliability, safety, and quality constraints.
OpenFlagship essay on tracing, replaying, and debugging agent behavior before failures scale.
OpenFeatured work
Selected professional themes, described without employer-confidential details. The strongest thread is platform leverage: turning low-level silicon behavior into repeatable workflows engineers can use.
repeatable debug workflow / platform observability / silicon readiness
Built and maintain internal scan-debug tooling used by multiple engineering teams to support deterministic state capture and root-cause workflows.
Work across DFX, design, verification, bring-up, and debug stakeholders to improve observability, readiness, and platform reliability for next-generation AI/HPC silicon programs.
Focus on making complex hardware systems observable, debuggable, and reliable through state capture, test access, and engineering productivity tooling.
Current focus
Core practice means direct professional or published work. Emerging research arcs means active study, writing, and future work.
Core practice
Emerging research arcs
State capture, scan access, JTAG/TDI-based workflows, MBIST context, and platform readiness.
Failure modes, telemetry, containment, auditability, and cyberphysical risk evaluation.
Useful output cost, latency, reliability, safety constraints, and infrastructure productivity.
Control planes, accelerated classical co-processing, observability, and integration bottlenecks.
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