Work

Hardware debug platforms for next-generation AI/HPC systems.

Work at the intersection of DFX methodology, scan/JTAG-based debug, pre-silicon verification, bring-up readiness, and engineering productivity tooling.

NVIDIA

Senior DFX Methodology Engineer, AI Hardware / Silicon Debug Platforms

I work on DFX methodology, scan/JTAG-based debug, MBIST, pre-silicon verification, and debug infrastructure for next-generation AI/HPC silicon systems.

Built and maintain internal scan-debug tooling used across multiple engineering teams for state capture and debug workflows.
Enable engineers to freeze system state, control scan/debug flows, and capture functional state through scan chains for root-cause analysis.
Work across DFX, design, verification, bring-up, and debug stakeholders to improve observability and platform readiness.
Develop methodology around scan access, JTAG/TDI-based capture, MBIST, and test/debug infrastructure.
Contribute to pre-silicon verification and readiness for advanced AI/HPC accelerator programs.
Translate low-level silicon behavior into usable workflows for cross-functional engineering teams.

Earlier work

Systems thinking before silicon observability.

Older roles are framed as foundations: manufacturing discipline, verification habits, tooling, product constraints, and field execution.

2018 - 2024

Intel: DFT / ATE / Product Debug

Worked across production test, scan debug, yield improvement, coverage analysis, data-driven factory debug, and automation across silicon products.

2020 - 2021

Materials and manufacturing R&D

Built advanced manufacturing workflows for 3D printed medical devices, connecting materials science, simulated process optimization, and measurable product quality.

2015 - 2021

Education systems operator

Co-founded and operated a rural education initiative, approaching delivery under constraint as an infrastructure and operating-model problem.

Next step

For roles or conversations around AI hardware observability.

Contact View labs